Non-volatile memory systems, such as memory cards, solid state drives (SSDs) or embedded non-volatile memories (such as iNAND), are typically formed of a controller circuit and a number of memory chips. These memory chips are connected to the controller over a bus structure, where it is common for multiple memory chips to share a common bus structure having shared ready/busy (R/B) line. For example, a single ready busy line can be shared by up to 16 dies, where only the actively selected die (including the chip enable (CE)) can use the ready/busy line at any given time. A baseline method of checking if a die is ready is by selecting the die and then sampling or polling the ready/busy signal. An alternative design is to select a die then use the check status command across the data bus to check a die's status. However, constant polling is inefficient and leads to higher power consumption. Cycling through dies selecting dies to check the status adds latency and increases power. In older memory systems, as instructions for similar operations were typically issued serially through the set of dies, this was not so much of limitation, but as memory die become more autonomous and their operations vary more in timing, this situation has become limiting on memory systems.
According to a first set of general aspects, a non-volatile memory system includes a plurality of memory circuits, each including one or more arrays or non-volatile memory cells, and a controller circuit to control the transfer of data between the memory circuits and a host connected to the memory system and to manage the storage of data on the memory circuits. A bus structure connects the controller circuit with the memory circuits, where the bus structure includes a common first bus line on which the memory circuits indicate to the controller circuit their ready/busy status. Each of the memory circuits indicates its ready/busy status by application of a pulse to the first bus line.
Further aspects relate to a non-volatile memory circuit having an array of non-volatile memory cells and read-write circuitry connected to the array. The memory circuit also has a plurality of contact pins, including a first pin, and a cache memory to store data being transferred between the pins and the array. A state machine on the memory circuit indicates the ready/busy status of the memory circuit on the first pin according to one or more modes, including a first mode wherein ready/busy status is indicated by a pulse settable to one of a plurality of durations.
Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, whose description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.